1. Technical Field
The embodiments described herein relate to an Externally Asynchronous-Internally Clocked (EAIC) system, and more particularly, to an EAIC system that internally generates a clock signal in an asynchronous system.
2. Related Art
An externally asynchronous-internally clocked (hereinafter, referred to as “EAIC”) system, which is operated externally in an asynchronous manner and operated internally on the basis of a clock, has been introduced in recent years for use in conventional semiconductor devices.
FIG. 1 is a conceptual block diagram of a general EAIC system 1. Referring to FIG. 1, an EAIC system 1 includes a first shift register block 2, a next input signal generating block 3, a second shift register block 4, an output buffer 5, a clock signal control block 6, and a clock signal generating block 7. The EAIC system 1 performs synchronous and asynchronous operations at the same time. In conventional EAIC systems, there is only outside visibility to the external input signals “INPUT” and external output signals “OUTPUT”. However, that the EAIC system also generates an internal clock “CLK” using an input signal.
Specifically, when an external input signal “INPUT” is supplied to the EAIC system from the outside, signals output from the first shift register block 2 are transmitted to the next input signal generating block 3. The next input signal generating block 3 generates input signals, which are to be sent to the second shift register block 4, using the received signals. The second shift register block 4 receives the signals and provides output signals. Accordingly, the output buffer 5 buffers the signals, which are provided from the first and second shift register blocks 2 and 4, and generates external output signals “OUTPUT”. In this case, the signals supplied from the second shift register block 4 are fed back to the next input signal generating block 3, so that new input signals to be sent to the second shift register block 4 may be generated.
Meanwhile, each of the first and second shift register blocks, 2 and 4 of the EAIC system 1, generates a ready signal “R” unlike a general register. That is, the ready signal “R” is a signal indicating that the first and second shift register blocks have completely transmitted a signal to the next circuit block. The clock signal control block 6 performs the logical operation of the ready signal “R”. Since the ready signal “R” is generated by the operation of the first and second shift register blocks 2 and 4 with a predetermined small time difference, the clock signal generating block 7 can generate an internal clock “CLK” based on the time difference. However, the clock signal control block 6 generally uses a NOR gate. Due to the structure of the NOR gate, NMOS transistors are connected in parallel and PMOS transistors are connected in series. For this reason, a series signal path of the PMOS transistor is lengthened in accordance with the number of signals to be received. Accordingly, output time may be delayed. That is, a general NOR gate may have restriction on fan-in due to the turn-on time of the PMOS transistors connected in series.
Accordingly, a conventional EAIC system 1 uses a wide NOR gate that is embodied as shown in FIG. 2. The wide NOR gate is a logic embodied so that only input signals of NMOS transistors connected in parallel are activated by substituting the PMOS transistors connected in series with one PMOS transistor. The clock signal control block 6 combines ready signals (“R0”-“R3”; four ready signals are exemplified for convenience of description) generated from the register blocks 2 and 4, and provides an output signal “R_OUT”. The clock signal control block 6 includes a PMOS transistor WP1 and first to fourth NMOS transistors NM1 to NM4 that receive the ready signals “R0” to “R3”.
The PMOS transistor WP1 includes a source connected to an external power supply voltage VDD, a gate connected to a ground voltage VSS, and a drain connected to a node a. Further, the PMOS transistor WP1 may be a weak PMOS transistor where weak current flows due to a long channel length. The first to fourth NMOS transistors NM1 to NM4 are connected in parallel, and include gates for receiving the first to forth ready signals “R0” to “R3”, drains connected to the node a, and sources connected to the ground voltage VSS, respectively.
The operation of the clock signal control block 6 will be described below. The clock signal control block provides an output signal “R_OUT” by the ready signals “R0” to “R3” that are activated with very small time difference. That is, since the ready signals “R0” to “R3” are activated or deactivated with a very small time difference, the clock signal control block 6 sets this as a target operation. Accordingly, the clock signal control block 6 is provided to output a low-level output signal “R_OUT” when all of the ready signals “R0” to “R3” are activated, and to output a high-level output signal “R_OUT” when all of the ready signals “R0” to “R3” are deactivated. For this reason, the NMOS transistors NM1 to NM4 are sequentially turned on by the ready signals “R0” to “R3” that are activated with very small time difference, and provide low-level output signals “R_OUT”.
Alternatively, all of the NMOS transistors NM1 to NM4 are turned off by the ready signals “R0” to “R3” that are activated with very small time difference and the PMOS transistor WP1 may provide a high-level output signal “R_OUT”. However, even though one NMOS transistor NM1 of several NMOS transistors is turned on, the PMOS transistor WP1 is turned on. Therefore, a direct current path is formed from the external power supply voltage VDD to the ground voltage VSS, so that large current may flow. That is, since the ready signals R0 to R3 are activated, a direct current path is always formed. Accordingly, the response speed can be improved as compared to a general NOR gate. However, since direct current flows, the current consumption may be large.